Principal SoC Design Engineer

Job Title

Principal SoC Design Engineer

Role Summary

Senior RTL/SoC engineer responsible for integrating IPs and developing subsystem microarchitecture and RTL for sophisticated processing systems used in IoT, automotive, and infrastructure applications. The role works on cross-functional teams to optimise performance, power and area (PPA) and to deliver robust subsystems into SoC platforms.

Work is collaborative and global, involving specification, verification review, performance analysis and close interaction with IP teams and project management.

Experience Level

Senior / Principal level. No explicit years-of-experience requirement stated in the posting.

Responsibilities

The role's core responsibilities are system- and subsystem-level design, integration and delivery.

• Integrate incoming IP blocks and define how they interwork within subsystems and SoCs.
• Develop subsystem microarchitecture specifications and implement RTL.
• Review verification plans, assist debugging and resolve functional and integration issues.
• Collaborate with performance analysis teams to evaluate and improve system PPA.
• Run design checks (CDC, RDC, X-prop, lint) and participate in synthesis and timing analysis flows; fix resulting issues.
• Propose refinements to IP teams based on system-level integration and usage.
• Identify and implement improvements to design methodologies and flows.
• Provide technical guidance to team members and support project planning and schedule management.

Requirements

Must-have:

• Proven experience in digital hardware design and RTL implementation using Verilog.
• Detailed understanding of methods and techniques for complex SoC development.
• Experience with static design checks (CDC, RDC, X-prop, lint).
• Ability to create clear design specifications.
• Proficiency with scripting languages such as Perl or Python.
• Strong delivery record of sophisticated RTL subsystems within project timescales.
• Ability to evaluate and make high-level PPA trade-offs and articulate the rationale.
• Experience with synthesis, timing analysis and power management techniques.
• Good communication and collaboration skills.

Nice-to-have / Preferred:

• Experience with ARM-based designs and ARM system architectures.
• Knowledge of memory system interconnect protocols (e.g. AMBA ACE-Lite, AXI).
• Familiarity with processor subsystems, NoCs, security subsystems, PCIe and system power management flows.
• Experience with SystemVerilog and verification methodologies.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related technical field, or equivalent practical experience. (The original posting explicitly states a Bachelor's or Master's is acceptable and that equivalent experience can be used in place of the degree.)

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.