Job Title
Principal Silicon Design Verification Engineer
Role Summary
Senior individual contributor on the Compute Silicon & Manufacturing Engineering team, responsible for pre-silicon verification and firmware-driven test content for security IP, subsystems, and SoC integration. The role supports verification strategy from early design through tapeout and silicon bring-up.
Experience Level
Senior / Principal level. Typical experience expectations are multi-year senior engineering experience (often 8+ years depending on degree and background).
Responsibilities
Primary responsibilities include ownership of verification strategy, test content, and cross-team delivery for IP and SoC projects.
- Develop C/C++ based test content for subsystems and SoCs, including bare-metal bring-up, directed and constrained-random tests, and self-checking tests for flows like secure boot and key/fuse management.
- Build and maintain C test infrastructure: startup code, low-level drivers, register access layers, and build flows (Makefiles, linker scripts, toolchain setup).
- Define and execute pre-silicon verification strategy for security IP blocks and their SoC integration, from planning through signoff and silicon bring-up.
- Architect and extend SystemVerilog/UVM environments that integrate C-based stimulus with testbenches to run processor-driven and stimulus-driven scenarios together.
- Drive coverage signoff across functional, code, and power-aware coverage; set goals, investigate gaps, and apply constrained-random, formal, and gate-level techniques.
- Act as verification lead and technical point of contact for customers and partner teams; own milestone delivery at IP and SoC levels.
- Mentor and review work of junior engineers, establish verification best practices, and onboard new team members.
- Improve verification efficiency through automation, reference/prediction models, debug tooling (Python), and correlation with FPGA prototyping for firmware bring-up and post-silicon validation.
Requirements
Must-have technical skills and role expectations, followed by desirable skills.
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Must-have: Extensive pre-silicon verification experience for IP, subsystems, and SoCs, including test planning, environment architecture, and coverage signoff.
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Must-have: Strong experience creating C/C++ test content and integrating embedded tests with SystemVerilog/UVM testbenches.
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Must-have: Proven ability to lead delivery and collaborate across architecture, design, DV, and firmware teams; strong debugging skills for complex designs.
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Must-have: Experience with coverage-driven verification and use of formal and gate-level techniques to close verification gaps.
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Must-have: Scripting and automation experience (e.g., Python) for tooling, automation, and result correlation.
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Nice-to-have: Experience with emulation, FPGA prototyping, RTL for FPGA/emulation, or post-silicon validation.
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Nice-to-have: Familiarity with assembly/startup code, linker scripts, Makefile build flows, and firmware bring-up practices.
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Nice-to-have: Knowledge of industry protocols (AMBA/AXI/AHB/APB, JTAG, SPI, I2C/I3C, USB) and hands-on hardware debug tools (JTAG debuggers, logic analyzers, oscilloscopes).
- Willingness and ability to meet required security screening and export-control eligibility checks.
Education Requirements
Doctorate, Master’s, or Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field are listed with experience-based alternatives (e.g., PhD + 3+ years, MS + 6+ years, BS + 8+ years) or equivalent experience. The posting explicitly permits equivalent practical experience in lieu of a degree.
About the Company
Company: Microsoft
Headquarters: Redmond, Washington, United States
Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.

Date Posted: 2026-06-19