Principal Silicon Design Verification Engineer

Role Summary

We are seeking a Principal Design Verification Engineer to join the Network Technology Solutions Group in the Data Center Solutions Group at AMD's office in Edinburgh. This position involves developing RTL blocks and subsystems for the AMD Pensando AI NIC product line, aimed at enhancing GPU clusters for large-scale AI training and inference workloads.

Experience Level

This is a senior-level position requiring significant experience in design verification, particularly in the context of ASIC and FPGA technologies.

Responsibilities

As the Principal Design Verification Engineer, your responsibilities will include:

• Leading verification efforts to functionally validate complex RTL blocks for next-generation Data Center networking ASICs.

Requirements

The ideal candidate will possess the following:

• Experience working as a technical lead in a verification team.
• Proven track record in simulation-based verification for ASIC or FPGA blocks and subsystems.
• Strong expertise in UVM-based verification in SystemVerilog, with comprehensive knowledge of the framework.
• Experience achieving verification coverage closure in ASIC or FPGA projects.
• Exceptional problem-solving abilities.
• Familiarity with Synopsys functional verification tools is advantageous.
• Experience with full chip verification is a plus.
• Knowledge of formal verification techniques is beneficial.
• Familiarity with AI-based debug techniques is a plus.
• Proficiency in Python and experience in C/C++ are advantageous.
• RTL design experience is preferred.
• Experience in networking technologies and products would be an advantage.

Education Requirements

A minimum of a Degree or Master's in Electronic Engineering, Computer Science, or a related field is required.