Principal SI/PI Engineer

Job Title

Principal SI/PI Engineer

Role Summary

Lead signal and power integrity (SIPI) engineering for high-speed SerDes interfaces across silicon, interposer, package, PCB, connectors, and compliance fixtures. Drive channel modeling, simulation-to-hardware correlation, signoff criteria, and laboratory validation while partnering with circuit, package, board, and product teams.

Provide technical leadership: mentor engineers, standardize SIPI flows and documentation, and influence architecture and design decisions to enable robust, high-performance interconnects.

Experience Level

Senior — requires 12+ years of relevant experience in high-speed SI/PI for SerDes links (silicon, package, and board), preferably in interface IP or high-volume product development.

Responsibilities

Accountabilities and day-to-day activities:

• Lead end-to-end SIPI for high-speed interfaces (PCIe Gen6/7/8, E224G, E448G, CXL over PCIe, and other SerDes links).
• Perform and drive channel modeling and correlation across time- and frequency-domain analyses (S-parameters, TDR, crosstalk, jitter/noise, BER/eye margining).
• Own SI signoff methodology: model extraction, quality checks, de-embedding, and ensuring models meet bandwidth requirements for target data rates.
• Partner with circuit/PHY, package, board, and product teams to diagnose bring-up and lab issues and propose quantifiable design fixes.
• Plan and execute bench characterization and compliance testing; guide fixture design and de-embedding/measurement calibration; document reusable learnings.
• Define, improve, and document SIPI flows, requirements, and checklists; lead technical reviews and mentor team members.
• Provide cross-program technical leadership: prioritize work, identify reuse opportunities, and influence architecture related to SI/PI.

Requirements

Must-have technical skills and experience. Nice-to-have items listed separately.

• Extensive practical experience with SI/PI for SerDes links across silicon, package, and board; demonstrated end-to-end delivery and correlation to hardware.
• Strong fundamentals in electromagnetic theory, transmission lines, passive/active modeling, and statistical link analysis; able to translate system requirements into measurable signoff criteria.
• Deep knowledge of high-speed link concepts: insertion/return loss, impedance control, mode conversion, NEXT/FEXT, jitter/noise sources, equalization (TX/RX FFE/DFE/CTLE), and BER analysis.
• Proven expertise with simulation and EM tools and model formats (examples: HSPICE, Keysight ADS/SystemVue, Ansys HFSS/SIwave/AEDT, Cadence Sigrity, Touchstone, IBIS-AMI, SPICE, EM-based RLGC).
• Hands-on lab and measurement experience: TDR, VNA, eye/jitter measurements, de-embedding, fixture calibration, and working with validation/compliance teams.
• Proficiency in scripting and automation to enable flows (Python preferred); disciplined approach to documentation and reproducibility.
• Demonstrated technical leadership: mentoring, design reviews, cross-functional influence, and clear communication to mixed audiences.

Nice-to-have:

• Experience with MATLAB or TCL for analysis and automation.
• Prior work focused on interface IP development and high-volume productization.

Education Requirements

B.S. in Electrical/Electronic Engineering or a related field is required; M.S. or Ph.D. preferred.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.