Principal RTL Verification Engineer

Role Summary

The Principal RTL Verification Engineer will be responsible for overseeing the IP and SoC Verification Methodologies and Environment for Impinj's next-generation Reader ICs. This entails guiding the entire verification process from conceptualization to production.

Experience Level

This position requires 15+ years of relevant industry experience, specifically in the realm of mixed signal IP and SoC RTL verification, particularly for complex multi-clock and multi-power domain SoCs.

Responsibilities

The core responsibilities of this role include:

• Developing a UVM-based IP and SoC verification framework to ensure production-worthy silicon.
• Creating a modular, scalable verification methodology allowing for the integration of Analog and Digital IPs across Reader IC products.
• Leading the definition of verification infrastructure such as coverage tools and test benches.
• Mentoring team members and collaborating with other engineering teams to deliver new features.
• Evaluating design verification plans and supporting the continuous improvement of existing products.

Requirements

Successful candidates will have:

• A Bachelor’s degree in electrical or computer engineering or relevant experience.
• Extensive experience with UVM and UPF methodologies.
• Hands-on experience defining verification strategies and developing integrated testing approaches.
• Proficiency in scripting languages like Python or Perl.
• Excellent communication skills and mentoring capabilities.

Education Requirements

Bachelor’s degree in electrical or computer engineering or equivalent practical experience is required.