Principal RTL Engineer

Role Summary

Lattice Semiconductor is seeking a Principal RTL Engineer to join the EDA tools development team in Pune. This position involves leading the design and development of FPGA debug engines within the Lattice EDA suite.

Experience Level

12+ years of experience in RTL System Design and EDA.

Responsibilities

• Lead the design and development of FPGA debug engine in Lattice EDA suite.
• Architect and refactor the FPGA debug IP and guide the UI team to enhance existing functionality and new features.
• Generate functional architecture and specifications for new FPGA debug IP functionality and guide the QA teams.
• Mentor and guide junior RTL & UI engineers working on FPGA debug IP.
• Maintain high standards of architecture, implementation quality, performance, and reliability.
• Improve development methodologies and processes.

Requirements

• Master’s in Electrical engineering/Computer engineering or related field.
• Strong communication skills.
• Expertise in HDL languages (Verilog/System-Verilog and VHDL).
• At least 15 years of Hardware design experience.
• At least 10 years of Hardware Design experience using FPGAs.
• At least 5 years on FPGA debugging methodologies.
• Proficiency in synthesis tools and simulation tools from leading EDA vendors.
• Proficiency in testbench/test-vector creation.
• Proficiency in C/C++, TCL, Python languages.
• Familiarity with protocols such as Serdes interface, Ethernet, PCIe, or Memory DDR.

Education Requirements

Master’s degree in Electrical engineering/Computer engineering or a related field required.