Principal Product Validation Engineer
Cadence Design SystemsJob Title
Principal Product Validation Engineer
Role Summary
The Principal Product Validation Engineer will work on validating complex digital systems and assist in developing innovative technologies within the verification domain. The role involves using various languages and tools for effective simulation and emulation processes.
Experience Level
Senior level with significant industry experience required.
Responsibilities
The candidate will be responsible for the following:
- Utilizing HDLs such as Verilog and/or VHDL for simulation and emulation.
- Debugging design/verification problems using EDA tools.
- Automating processes through scripting.
- Conducting functional verification of systems like SoC Verification with HVLs such as SystemVerilog.
- Designing and implementing complex functional verification environments.
- Working with protocols like PCIe, USB3/4, DP.
Requirements
Key qualifications include:
- Electrical, Electronics, or Computer Science Engineering degree.
- Proficient in HDLs (Verilog and/or VHDL).
- Experience with EDA tools and debugging.
- Scripting skills for process automation.
- Knowledge of SystemVerilog, C++, UVM.
- Familiarity with advanced protocols (PCIe, USB3/4, DP) is a plus.
Education Requirements
Bachelor's degree in Electrical, Electronics, or Computer Science Engineering is required.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
