Principal Product Engineer - DDR IP

Job Title

Principal Product Engineer — DDR IP

Role Summary

Serve as the primary technical interface for strategic customer engagements to deploy and debug Cadence DDR PHY IP solutions. This is a hands-on, post‑silicon engineering role within the DDR IP Product Engineering team based in Shanghai focused on silicon bring‑up, customer support, and cross‑domain issue resolution.

Experience Level

Senior-level. Typical guidance in this posting: M.S. plus ~10+ years relevant experience, or Ph.D. plus ~5+ years relevant experience.

Responsibilities

Key responsibilities include providing technical leadership for customer deploy and debug activities and owning post‑silicon support cases.

• Act as primary technical liaison for debugging customer silicon issues (systems and ATE) and coordinate cross‑functional resolution.
• Perform post‑silicon bring‑up and hands‑on debug of DDR/LPDDR/GDDR PHY implementations.
• Reproduce and analyze customer failures in the lab using oscilloscopes, BERTs, protocol exercisers, and protocol analyzers.
• Diagnose signal integrity (SI) and power integrity (PI) related hardware issues affecting IP behavior.
• Own and manage customer support cases using case management and tracking tools (SFDC, Sherlock, JIRA).
• Provide onsite customer support and debug at customer sites (~10% travel).
• Leverage AI tools and analytics to accelerate debugging, extract insights from complex datasets, and improve deliverables.

Requirements

Must-have technical skills and experience; brief list of preferred items follows.

• Proven experience with Memory PHY, memory controller interactions, and DRAM behavior.
• Experience with advanced mixed‑signal verification and system‑level simulation tools.
• Strong debugging and problem‑solving skills in post‑silicon environments.
• Hands‑on experience with lab equipment to reproduce and analyze failures (oscilloscopes, BERTs, protocol exercisers, analyzers).
• Familiarity with SI/PI analysis concepts and ability to diagnose related hardware issues.
• Experience managing support cases and coordinating fixes across teams using tools such as SFDC, Sherlock, and JIRA.
• Strong presentation and written/verbal communication skills for technical customer interactions.
• Nice-to-have: familiarity with advanced process nodes (7nm and below).

Education Requirements

Posting specifies either an M.S. in Electrical/Computer Engineering (or similar) with ~10+ years of relevant experience, or a Ph.D. with ~5+ years of relevant experience. Related technical degrees in electrical/computer engineering or similar fields mentioned.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.