Principal Physical Design Engineer

Role Summary

A Principal Physical Design Engineer will own and execute the physical implementation of advanced digital ICs from netlist to GDSII, ensuring optimal power, performance, and area while maintaining robust sign-off quality. The emphasis is on hands-on technical expertise and direct execution of complex implementation tasks over management responsibilities.

Experience Level

Senior level; 10+ years of relevant experience is required.

Responsibilities

The key responsibilities include:

• Lead and perform all major steps of the digital physical design flow, including block-level and top-level floorplanning, placement, clock tree synthesis, routing, and timing closure.
• Collaborate directly with RTL and synthesis teams for timing constraint setup, synthesis refinement, and netlist quality.
• Develop and implement strategies for power integrity, IR-drop analysis, EM verification and low-power physical design using UPF/CPF methodologies.
• Hands-on execution of physical verification: DRC, LVS, ERC, antenna checks, reliability and manufacturability checks, and ECO implementations.
• Drive timing analysis and closure at all implementation stages, using static timing analysis (STA) and advanced node-specific signoff flows.
• Own integration of hard macros, blocks, and IP; define and optimize power grid, pad ring, and custom routing as required.
• Propose and develop automation for various physical design flows using TCL, Python, or other scripting languages for process improvement.
• Perform design partitioning, floorplan, and chip assembly for hierarchical and complex designs targeting advanced process nodes (≤ 7nm).
• Interface with DFT, signal/power integrity, package, and test teams to ensure comprehensive signoff and manufacturability.
• Actively contribute to methodology improvements, flow development, and CAD tool evaluations.
• Participate in engineering and peer reviews, providing direct, hands-on technical guidance to the team.

Requirements

The ideal candidate must possess the following qualifications:

• Bachelor’s or Master’s in Electrical/Electronics/VLSI Engineering or a related discipline.
• 10+ years’ hands-on experience in all aspects of digital physical design for ASIC/SoC development; experience with advanced FinFET nodes is a plus.
• Expert knowledge of EDA tools for physical design: Cadence Innovus, Synopsys ICC2, Mentor Olympus, STA tools.
• Deep technical expertise in timing closure, PPA optimization, physical verification, and IR-drop/EM checks.
• Scripting skills in TCL, Python, or Perl for workflow automation and data analysis.
• Proven track record of successful tapeouts (block and full chip) at advanced nodes, including hierarchical and top-level physical implementation.
• Experience with low-power design techniques and physical implementation of complex multi-power/voltage domain chips.
• Strong debug and analytical skills, including post-route timing, layout closure, and design ECO execution.
• Excellent ability to document flows and report findings.

Education Requirements

Bachelor’s or Master’s in Electrical/Electronics/VLSI Engineering or a related discipline.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.