Principal Physical Design Engineer

Job Title

Principal Physical Design Engineer

Role Summary

Lead technical execution and methodology for advanced DRAM digital physical design from RTL through tapeout. Focus areas include timing closure, power integrity, EMIR analysis, and design reliability.

Collaborate with architecture, RTL, implementation, CAD, and technology teams to deliver scalable physical design solutions that meet power, performance, area (PPA), and reliability targets. Mentor engineers and drive methodology innovation across the organization.

Experience Level

Senior level — requires extensive experience. Typical background: Master's in Electrical Engineering + 8+ years, or Bachelor's + 10+ years in ASIC physical design (see Education Requirements for details).

Responsibilities

Accountable for physical implementation and signoff of complex DRAM digital designs and for improving design and signoff methodologies.

• Lead floorplanning, place-and-route, clock tree synthesis, timing closure, and tapeout activities for block and full-chip designs.
• Define and execute power integrity strategies: PDN planning, IR drop analysis, EM verification, and EMIR signoff.
• Resolve timing, congestion, power, signal integrity, and reliability issues across teams and design stages.
• Develop and deploy methodology improvements, automation, and guidelines to increase scalability and build quality.
• Mentor engineers, provide technical leadership, and influence physical design roadmaps for next-generation memory products.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Proven expertise in physical design implementation flows: floorplanning, P&R, CTS, timing closure, and signoff.
• Hands-on experience with STA, signal integrity, power integrity, physical verification, and advanced process technologies.
• Proficiency with industry-standard implementation and signoff tools (e.g., Synopsys ICC2/Fusion Compiler, PrimeTime, PrimePower, RedHawk, or equivalents).
• Strong scripting and automation skills (Python, Tcl, or similar).
• Demonstrated ability to drive cross-functional technical initiatives and influence engineering organizations.

Nice-to-have:

• Experience developing PDN, EMIR, or large-scale physical design methodologies for ASICs, SoCs, or memory products.
• Expertise in static/dynamic IR drop, electromigration verification, current profiling, and IDD modeling.
• Track record of methodology transformation, tool deployment, and process improvement across organizations.
• Experience applying AI-assisted tools or Generative AI to improve engineering efficiency is a plus.

Education Requirements

Master's degree in Electrical Engineering (or equivalent) with 8+ years of relevant experience, OR Bachelor's degree with 10+ years of relevant ASIC physical design experience; equivalent practical experience accepted.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.