Principal Physical Design

Job Title

Principal Physical Design Engineer

Role Summary

Lead technical execution and methodology for advanced DRAM digital physical design from RTL through tapeout. primary focus areas include timing closure, power integrity, EMIR analysis, and design reliability for next-generation memory products.

Work across architecture, RTL, implementation, CAD, and technology teams to deliver scalable physical design solutions, mentor engineers, and influence the physical design and power-integrity roadmap.

Experience Level

Senior — typically requires 8–10+ years of ASIC/physical design experience. Company specifies Master's +8 years or Bachelor's +10 years (see Education Requirements).

Responsibilities

Accountable for end-to-end physical design delivery and methodology leadership.

• Lead physical implementation of complex DRAM digital blocks and full-chip flows: floorplanning, placement, clock tree synthesis, timing closure, and tapeout.
• Define and drive power integrity and EMIR signoff strategies, including PDN planning, IR drop analysis, and electromigration verification.
• Collaborate with cross-functional teams to resolve timing, congestion, power, signal integrity, and reliability issues at block and chip level.
• Develop and deploy methodology improvements and automation to improve build quality, efficiency, and scalability.
• Mentor engineers and provide technical leadership across projects and product generations.

Requirements

Core technical skills and practical experience required.

Must-have:

• Expertise in physical design flows: floorplanning, place & route, clock tree synthesis, timing closure, and design signoff.
• Hands-on experience with static timing analysis, signal integrity, power integrity, physical verification, and advanced process technologies.
• Proficiency with industry physical-design and signoff tools (examples: Synopsys ICC2/Fusion Compiler, PrimeTime, PrimePower, RedHawk, or equivalents).
• Strong scripting and automation skills (Python, Tcl, or similar).
• Proven ability to drive multi-functional technical initiatives and influence engineering organizations.

Nice-to-have:

• Experience developing PDN, EMIR, or power-integrity methodologies for large ASIC/SoC/memory designs.
• Expertise in static/dynamic IR drop analysis, current profiling, IDD modeling, and electromigration verification.
• Experience leading methodology transformation, tool deployment, and cross-organization process improvements.
• Experience applying AI-assisted tools to improve engineering efficiency.

Education Requirements

Master's degree in Electrical Engineering (or equivalent) with 8+ years of relevant experience, or Bachelor's degree with 10+ years of relevant ASIC physical-design experience. Equivalent practical experience will be accepted where indicated.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.