Principal/Manager - NPU Design Implementation (Synthesis)
QualcommJob Title
Principal/Manager - NPU Design Implementation (Synthesis)
Role Summary
Lead synthesis and timing-closure for Neural Processing Unit (NPU) IP and subsystems within SoC development. Work with RTL, architecture, STA and physical design teams to deliver optimized gate-level netlists for advanced process nodes.
Experience Level
Senior - expects substantial technical and leadership experience. The posting specifies ~15+ years in ASIC synthesis and timing closure with at least 3 years in NPU or AI processor design; alternative degree-plus-experience combinations are listed under Education Requirements.
Responsibilities
Primary responsibilities include synthesis ownership, timing closure, PPA optimization, and cross-functional collaboration.
- Lead RTL-to-gate-level synthesis for NPU IP and subsystems using tools such as Synopsys Design Compiler and Cadence Genus.
- Drive pre-layout and post-layout timing closure across multiple voltage and process corners; collaborate with STA to resolve setup/hold violations.
- Apply physical-aware synthesis techniques and low-power strategies (UPF/CPF, multi-voltage) to meet PPA targets.
- Validate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.
- Perform LEC, clock/power checks, linting, and other quality checks to ensure netlist readiness for P&R.
- Mentor junior engineers and drive synthesis/timing best practices across teams.
- Evaluate and adopt advanced synthesis methodologies and EDA tool capabilities to improve QoR.
Requirements
Must-have skills and experience:
- Strong knowledge of the ASIC flow: RTL → synthesis → STA → P&R.
- Proficiency with synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).
- Experience with UPF/CPF-based low-power flows and multi-voltage designs.
- Advanced scripting skills (Tcl, Perl, Python) for automation.
- Familiarity with EDA verification and analysis tools (Spyglass, lint, CDC, power analysis tools).
- Proven ability to lead synthesis teams and coordinate across RTL, DFT, STA, and physical design groups.
- Extensive ASIC synthesis and timing-closure experience; the posting specifies ~15+ years in ASIC synthesis with at least 3 years focused on NPU/AI processor design.
Preferred:
- Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.
- Prior tape-out experience for NPU or DSP cores.
Education Requirements
The posting specifies a Bachelor’s, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related field with experience: Bachelor’s + 4+ years, Master’s + 3+ years, or PhD + 2+ years. Equivalent practical experience is accepted per the minimum-qualifications language.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
