Principal Layout Engineer

Role Overview

The Principal Layout Engineer will be part of the Memory Interconnect Design team located in San Jose, California. This role focuses on crucial Analog/Mixed-signal product designs, reporting directly to the Director of Design Engineering.

Experience Level

Looking for candidates with a minimum of 6 to 8 years of relevant experience, depending on educational qualifications.

Key Responsibilities

• Take ownership of both block level and chip level layouts.
• Define the optimal layout floor plan and establish coordination with circuit/logic design teams regarding estimations and scheduling.
• Complete high-performance layouts in a timely manner.
• Review layouts created by contractors, ensuring adherence to established design practices.
• Deliver layouts that meet stringent performance and power requirements.
• Conduct layout verification using LVS, DRC, and ERC tools.
• Facilitate layout reviews to confirm that all design requirements have been met.

Qualifications

Candidates should possess a BS in Electrical Engineering with at least 8 years of experience or an MS with a minimum of 6 years in CMOS design layout. Experience with FinFET processes, Cadence Virtuoso tools, and strong layout techniques for device matching is required.

Education Requirements

Required: BS in Electrical Engineering or equivalent experience; MS preferred.