Principal Engineer - RTL Design

Role Overview

As a Principal Engineer specializing in RTL Design at Synopsys, you will be responsible for leading and executing complex design initiatives that ensure the delivery of high-performance, reliable, and innovative products.

Experience Level

This role requires senior-level expertise with a robust background in digital design and RTL architecture, aiming at those with substantial experience in the semiconductor industry.

Key Responsibilities

• Design and implement RTL code for high-performance circuits.
• Collaborate with cross-functional teams to define product specifications.
• Lead code reviews and set coding standards for the design team.
• Mentor junior engineers and provide guidance on best practices in RTL design.
• Participate in verification and validation processes to ensure design accuracy.

Essential Requirements

Candidates should possess a strong understanding of FPGA/ASIC design fundamentals and up-to-date knowledge of tools and methodologies used in RTL design.

Education Requirements

A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is required.