Principal Engineer, RTL ASIC Design

Role Summary

The Principal Engineer, RTL ASIC Design role involves verifying the circuitry for chips in the Infrastructure Processor Business Unit at Marvell. This position focuses on creating specifications, conducting reviews, and collaborating with cross-functional teams to ensure design compliance with customer needs.

Experience Level

Senior level with 12+ years of experience for Master's/PhD holders or 15+ years for Bachelor's degree holders.

Responsibilities

The key responsibilities include:

• Define sub-system architecture, micro-architecture, and register specifications for complex SoCs.
• Conduct performance and design requirement reviews with teams and customers.
• Implement specifications using RTL coding techniques.
• Collaborate with third-party vendors for IP customization.
• Guide physical design teams on various aspects of design.
• Work with verification teams on pre-silicon verification tasks.
• Mentor junior team members.

Requirements

Required qualifications include:

• Bachelor’s in Computer Science, Electrical Engineering, or related fields; Master's/PhD preferred.
• Experience in creating architecture and design specifications.
• Proficient in Verilog/System Verilog with System Verilog assertions.
• Expertise in high-speed memory protocols (DDR4/5, LPDDR4/5X, HBM3).
• Experience in network processors, switches, or SoCs.
• Familiarity with scripting languages such as Perl/Python/Shell is a plus.

Education Requirements

Expected education includes a Bachelor’s degree in Computer Science, Electrical Engineering, or related fields; advanced degrees are preferred.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.