Principal Engineer, Logic Design (Packet Processing)

Job Title

Principal Engineer, Logic Design (Packet Processing)

Role Summary

The Principal Engineer will design and implement RTL for high-performance Ethernet switch ASICs in the Core Switching Group. The role focuses on packet processing components and participates across the full ASIC program lifecycle, from micro-architecture and RTL implementation to timing closure, ECOs, and silicon bring-up.

Team context: the position sits in a cross-functional ASIC design organization targeting hyperscale data centers and cloud providers, working on high-performance merchant silicon for networking infrastructure.

Experience Level

Senior-level. Typically requires 8+ years of relevant ASIC digital design experience (or ~6+ years for candidates with an advanced degree); expects substantial RTL and packet-processing experience.

Responsibilities

The role covers end-to-end logic design and verification responsibilities. Key responsibilities include:

• Develop micro-architecture specifications for packet-processing blocks.
• Write efficient, synthesizable RTL (Verilog) for complex networking functions.
• Create and execute unit-level verification; participate in design reviews.
• Drive timing convergence and implement ECOs to meet performance targets.
• Debug RTL, perform root-cause analysis, and coordinate fixes across teams.
• Collaborate with architecture, verification, physical design, and software teams to deliver silicon.
• Contribute to low-power design, clock-domain crossing solutions, and production readiness.

Requirements

Must-have skills and experience:

• Proven experience in digital design on multiple networking ASICs.
• 4+ years of experience in Verilog-based RTL design or verification in deep submicron technologies.
• Familiarity with Ethernet and common networking protocols.
• Experience participating across the ASIC lifecycle: specification, RTL, verification, timing closure, ECO, and debug.
• Strong analytical problem-solving and ability to work independently at multiple abstraction levels.

Nice-to-have:

• Extensive experience with Ethernet, TCP/IP, MPLS, tunneling, and packet-processing architectures (parsing, ACLs, metering, policing).
• Experience achieving timing closure on high-performance ASICs and applying low-power design techniques.
• Experience with scripting languages such as Python or Perl for automation and analysis.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent. Hiring guidance in the posting: B.S. with 8 years of industry experience, or M.S. with 6 years of industry experience in digital design on multiple networking ASICs. Equivalent practical experience is accepted per the original posting.

Compensation and Benefits

Annual base salary range: $141,300 - $226,000. Eligible for discretionary annual bonus and equity awards per company plans. Benefits include medical, dental, vision, 401(k) with company match, ESPP, paid holidays, paid leave, and other standard benefits.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.