Principal Engineer - IP Design Verification

Job Title

Principal Engineer - IP Design Verification

Role Summary

Lead verification strategy and execution for DRAM analog and mixed-signal IPs (DDR5/LPDDR5/DDR6/LPDDR6), owning end-to-end verification, coverage, and sign-off across block, chip and power-up scenarios.

Work with global design and verification teams to mentor engineers, make architecture decisions, and deploy scalable verification and AI-assisted automation solutions.

Experience Level

Senior — 10–15 years of ASIC/SoC/Memory analog & mixed-signal verification experience with increasing technical responsibility.

Responsibilities

Primary responsibilities include verification planning, execution, sign-off, and team leadership:

• Define and own end-to-end verification strategy for DRAM analog and mixed-signal IPs, including block-level analog/digital verification, power-up flows, reliability/ESIRA simulations, behavioral models, and timing checks.
• Develop, review, and maintain verification plans to ensure completeness, risk mitigation, and alignment with design intent.
• Drive block-, top-level, and full-chip analog verification sign-off with corner coverage and quality closure.
• Define functional, code, and assertion coverage strategies and lead coverage closure efforts.
• Identify verification risks early and make architectural decisions to improve design quality.
• Mentor, train, and lead verification engineers and set direction for verification efforts across projects.
• Identify opportunities for AI-based automation and collaborate with cross-functional teams to deploy scalable, validated solutions.

Requirements

Must-have and preferred technical skills and experience (education listed separately):

• Must-have: Extensive experience mentoring/leading analog and mixed-signal block verification; strong analytical capability for CMOS and gate-level circuit verification; proficiency with SPICE/mixed-signal and digital simulations.
• Experience with memory technologies (DRAM, HBM, PHY, controller) or high-speed interfaces, and exposure to chip-level verification and multi-IP integration.
• Proficiency with tools such as Virtuoso, PrimeSim/FinSim, HSPICE, Xcelium, Simvision; hands-on experience writing Verilog models.
• Strong communication and debugging skills; ability to work effectively with globally distributed teams.
• Experience using AI-assisted tools to improve verification productivity, with emphasis on correctness, validation, and responsible use of enterprise-approved AI systems.
• Nice-to-have: Verilog-A/MS and RVM model writing; familiarity with Verdi/Verisium and advanced waveform/debug viewers.

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.