Principal Engineer in ASIC Physical Design

Role Summary

This position involves leading the physical implementation of complex Mixed Signal IPs and test chips, ensuring effective collaboration with cross-functional teams to integrate and verify designs. The role requires a deep understanding of the entire design cycle from RTL to GDSII, utilizing Synopsys tools and methodologies.

Experience Level

The ideal candidate should have over 10 years of experience specifically in physical design, with significant hands-on experience in IC implementation flows and deep submicron design methodologies.

Responsibilities

Key responsibilities include:

• Leading physical design implementations, from RTL to GDS, and ensuring project goals are met regarding timing and physical sign-off.
• Collaborating with various teams for the integration and verification of IP designs.
• Providing mentorship and technical direction to team members.
• Enhancing design methodologies and processes to improve efficiency and quality.

Requirements

Applicants should possess:

• An engineering degree (BE or MSEE) and over 10 years of relevant experience.
• Expertise in the full design cycle and strong knowledge of Physical Design methodologies.
• Advanced skills in PnR and sign-off processes (STA, PV, EMIR).
• Exceptional problem-solving skills and attention to detail.

Education Requirements

Applicants must hold a Bachelor’s or Master’s degree in Electrical Engineering or a related field.