Principal Engineer, Design For Test
Marvell TechnologyRole Summary
The Principal Engineer, Design For Test will be a key member of the Custom Silicon Engineering team at Marvell. This role focuses on architecting, leading, and implementing Design-for-Test (DFT) solutions for complex IP and SoC designs aimed at high-performance compute across various applications.
Experience Level
Senior; requires 10-15 years of experience in custom chip design and DFT.
Responsibilities
The responsibilities for this role include:
- Architecting and implementing DFT/Test on complex ASIC/SoC designs.
- Defining and executing DFT architectures and methodologies.
- Mentoring and guiding a team of engineers in DFT initiatives.
- Conducting post-silicon bring-up and debug for various designs/IPs.
- Enhancing DFT methodologies and tools.
Requirements
The ideal candidate should meet the following requirements:
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields; Master’s or PhD preferred.
- 10+ years of hands-on DFT experience in custom chip design.
- Experience in DFT execution stages: SCAN, MBIST, Validation, STA.
- Knowledge of DFT/Test architecture; involvement in DFT architecture definition for SoC designs.
- Prior leadership experience in ASIC design projects.
Education Requirements
Bachelor’s degree in Computer Science, Electrical Engineering, or related fields is required; advanced degrees are preferred.
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
