Principal Engineer - Design
MicrochipJob Title
Principal Engineer - Design
Role Summary
The Principal Engineer will join Microchip's Data Center Solutions (DCS) business unit to define architecture and lead RTL design for data center–class ASICs used in servers, storage, and hyperscale environments.
Focus areas include high-performance interconnects (PCIe, CXL, NVMe, SAS), flash controllers, switches, and memory infrastructure; the role drives design quality from micro-architecture through silicon bring-up.
Experience Level
Senior - typically requires 10+ years of ASIC or SoC digital design experience.
Responsibilities
Responsible for technical leadership, end-to-end RTL delivery, and cross-functional coordination to ensure high-quality silicon.
- Lead architecture and micro-architecture definition for complex IPs, subsystems, or full-chip designs.
- Drive RTL design execution from concept through synthesis, sign-off, and silicon bring-up support.
- Serve as a technical authority on digital design, optimizing performance, power, and area (PPA).
- Resolve cross-domain design and EDA tool issues that impact schedule or silicon quality.
- Collaborate with verification, physical design, DFT, system, and product teams for predictable delivery.
- Define low-power, high-performance design strategies for data-center workloads.
- Influence protocol and platform roadmap decisions related to PCIe, CXL, NVMe, SAS, and related interconnects.
- Mentor engineers and provide architectural reviews and design direction.
Requirements
Key technical requirements; items labeled "Nice-to-have" are not mandatory.
- Must-have: Strong SystemVerilog RTL design and micro-architecture development skills.
- Must-have: Proven record delivering multiple complex tape-outs in high-performance or data-center silicon.
- Must-have: Hands-on experience with lint, CDC, formal verification, logic synthesis, and static timing analysis.
- Must-have: Strong understanding of physical design interactions including timing, power, and congestion.
- Must-have: Experience with low-power design methodologies and flows.
- Must-have: Knowledge of DFT (scan, testability) and DFT sign-off interactions.
- Must-have: Proficiency in scripting languages (Tcl, Perl, Awk).
- Must-have: Hands-on experience with high-speed protocols such as PCIe, CXL, NVMe, SAS/SATA, or similar serial interfaces.
- Nice-to-have: Experience with AI-driven workflows to accelerate development.
- Nice-to-have: Experience with Cadence-based ASIC design environments.
Education Requirements
Bachelor's degree in Electronics or Electrical Engineering minimum.
About the Company
Company: Microchip
Headquarters: Chandler, Arizona, USA
Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.
