Principal Engineer - ASIC Digital Verification

Role Summary

The Principal Engineer position in ASIC Digital Verification will involve leading verification efforts for complex digital designs. You will be responsible for architecting and implementing advanced verification methodologies to ensure high-quality products. Strong collaboration with cross-functional teams will be essential to deliver projects on time.

Experience Level

This role is designated for professionals in the Senior level category, seeking individuals with substantial expertise in ASIC verification processes.

Responsibilities

• Design and implement verification strategies for ASIC projects.
• Lead and mentor a team of engineers in verification activities.
• Develop test plans, verification environments, and frameworks.
• Analyze and debug issues within the digital design and verification flows.
• Ensure adherence to quality and performance targets throughout the project lifecycle.
• Collaborate with design engineers to optimize for performance and functionality.

Requirements

• Master’s degree in Electrical Engineering or related field.
• Minimum of 5 years of experience in ASIC digital verification.
• Strong proficiency in Verilog/SystemVerilog and UVM.
• Extensive experience with simulation tools and debugging techniques.
• Ability to work independently and manage multiple priorities.

Education Requirements

A Master’s degree in Electrical Engineering or a related discipline is required for this position.