Principal Engineer - ASIC Digital Design Verification

Role Summary

This role involves leading high-level digital design verification initiatives focused on Interface IP protocols at Synopsys. You will utilize your expertise in digital design and verification methodologies to ensure high-quality, reliable ASIC designs that meet customer specifications.

Experience Level

The ideal candidate should possess significant experience as a Principal Engineer with a solid track record in designing, verifying, and implementing digital designs, particularly in the ASIC domain. Familiarity with System Verilog, UVM, and advanced verification techniques is essential.

Responsibilities

Your primary responsibilities will include:

• Designing and implementing robust verification environments for Interface IP protocols.
• Identifying and rectifying bugs in collaboration with design and architecture teams.
• Creating detailed test plans and functional coverage analysis to verify complex digital IP.
• Guiding junior engineers in best practices for verification methodologies.
• Conducting design and verification reviews with constructive feedback to enhance quality.
• Documenting design specifications, test plans, and verification reports.

Requirements

To qualify for this position, you should meet the following requirements:

• Strong proficiency in digital design and verification methodologies.
• Experience in developing testbenches utilizing System Verilog and UVM.
• Ability to use advanced verification techniques.
• Familiarity with scripting languages like Python or Perl for automation purposes.

Education Requirements

A bachelor’s degree in Electrical Engineering or a related field is typically required. Advanced degrees may be preferred based on the level of expertise needed for this position.