Principal Engineer, ASIC Digital Design

Role Summary

As a Principal Engineer in ASIC Digital Design, you will lead the integration of advanced test plans and verification for high-performance silicon chips, while also mentoring junior engineers and driving collaborations within the engineering team.

Experience Level

10+ years of experience in ASIC development and mixed-signal verification is required. Proficient knowledge of high-speed protocols such as PCIe and Ethernet, as well as digital signal processing, is crucial.

Responsibilities

• Implement Unified Test Plans for HPC DSP-based SERDES PHY products.
• Build and maintain verification environments leveraging UVM methodology and SystemVerilog.
• Develop and optimize automation scripts in Shell, Perl, Python, C++, and explore AI-driven automation approaches.
• Collaborate with stakeholders to resolve technical challenges and achieve project milestones.
• Create comprehensive test plans for high-speed data recovery circuits.
• Share knowledge and best practices among team members and project leaders.

Requirements

Requires advanced skills in SystemVerilog and UVM methodology, strong scripting proficiency, and organizational skills to manage tight deadlines. Effective communication and mentorship abilities are needed to foster a collaborative team environment.

Education Requirements

A degree in Electrical Engineering or a related field, combined with extensive professional experience, is preferred.