Principal Engineer, Advanced Package Technology
Marvell TechnologyJob Title
Principal Engineer, Advanced Package Technology
Role Summary
Lead development of advanced semiconductor package technologies (2.5D/3D, interposers, substrates, co-packaged solutions) to meet electrical, mechanical, thermal and manufacturability requirements for high-performance computing, AI accelerators and networking products.
Work within the Advanced Packaging R&D team and partner with silicon design, system/platform engineering, OSATs, foundries and substrate vendors to define architecture, validate manufacturability and drive technologies from proof-of-concept to productization.
Experience Level
Senior — role targets experienced candidates (typical guidance provided in Education Requirements: 8+ to 15+ years depending on degree level and prior roles).
Responsibilities
Primary responsibilities include technology roadmap, package architecture, co-design with silicon teams, and supplier/program management.
- Develop and maintain packaging technology roadmap for AI XPUs, XPU-attach and switches.
- Create new package technology concepts, perform routing feasibility, and run signal/power integrity studies to optimize designs.
- Define package architecture: chiplet topology, interposer/substrate scaling, PDN strategy, and thermal envelope.
- Lead co-design across silicon floorplanning, PDN modeling, mechanical and thermal reliability.
- Select package materials, define substrate stack-ups, and perform mechanical and reliability analysis.
- Work with OSATs, substrate manufacturers and foundries to evaluate process capability, manufacturability, yield and cost; drive package qualification to volume readiness.
- Guide measurement and validation activities (e.g., VNA/TDR) and correlate simulations with lab/board-level results.
- Manage cross-functional programs and influence internal and external stakeholders and suppliers.
Requirements
Must-have technical skills, tools experience, and professional capabilities. Nice-to-have items listed where applicable.
- Deep experience in advanced package and substrate technologies, process and materials, and component/board-level reliability, including warpage and thermal management (must-have).
- Strong expertise in signal integrity and power integrity: transmission-line behavior, electromigration, PDN strategy, and interface with memory/interposer/substrates/PCBs (must-have).
- Hands-on experience or demonstrated mastery in simulation and extraction tools: Cadence Sigrity (PowerSI), Ansys SIwave, Ansys HFSS, Cadence Clarity; ability to define which simulations are required and interpret results (must-have).
- Routing feasibility and layout experience using Cadence APD or PCB editor and knowledge of interposer/substrate/package/PCB design rules (must-have).
- Experience with packaging options such as CoWoS, EMIB, Co-packaged optics/copper, CPO/CPC and multi-chip configurations (must-have).
- Proven ability to convert open-ended concepts into proof-of-concept samples and productizable technologies, including IP creation and protection (must-have).
- Program and vendor management experience: drive supplier alignment, evaluate OSAT/foundry capabilities, and lead cross-company supplier programs (must-have).
- Strong communication, presentation and documentation skills; ability to work across multiple time zones and influence senior stakeholders (must-have).
- Nice-to-have: experience with system/rack-level integration, thermal/mechanical analysis, silicon disaggregation/re-aggregation and memory integration.
- Nice-to-have: hands-on VNA and TDR characterization experience for package and PCB validation.
Education Requirements
Degree or equivalent experience required: Bachelor's, Master’s, or PhD in Electrical Engineering, Mechanical Engineering, Materials Science or related technical field. Typical experience guidance stated in the posting: Bachelor's + ~15+ years, Master’s + ~10–12+ years, PhD or post-doc + ~8+ years (equivalent professional experience may be accepted in place of formal degree).
About the Company
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
