Principal Digital Engineer (DFT Design)

Job Title

Principal Digital Engineer (DFT Design)

Role Summary

Lead DFT design and implementation for automotive power-management ICs. Work with digital design, P&R, test engineering and validation teams to define and deliver DFT solutions that meet automotive test and ASIL requirements.

The role focuses on inserting and validating scan and LogicBIST, generating ATPG patterns, improving test coverage and reducing ATE time across pre- and post-layout flows.

Experience Level

Senior / Principal level. Typical experience expectation: MSEE with ~12+ years or BSEE with ~15+ years of relevant digital design and DFT experience.

Responsibilities

Core responsibilities include DFT implementation, validation, and cross-team integration.

• Insert DFT/scan on digital logic, perform ATPG and validate test patterns on pre- and post-layout gate-level netlists.
• Deliver and validate test patterns with Test Engineering; debug and fix scan pattern failures on ATE and silicon.
• Insert LogicBIST (Lbist) using industry-standard flows and tools; improve scan coverage and optimize pattern count to reduce ATE time.
• Participate in digital design flow activities: micro-architecture, design partitioning, RTL (Verilog/SystemVerilog), synthesis, timing constraints, timing analysis, lint, CDC, and interaction with P&R.
• Create and review DFT specifications and design documentation; organize and participate in design reviews and checklists.
• Collaborate with architects, design, P&R, test, and silicon validation teams to meet TEST and ASIL-B/D requirements.
• Work on-site three days per week as required.

Requirements

Must-have technical skills and experience; desirable items listed separately.

• Extensive hands-on experience with scan insertion, ATPG, and improving scan coverage.
• Experience inserting LogicBIST during synthesis or RTL flow and running gate-level simulations with test patterns.
• Practical RTL coding experience and synthesis exposure; understanding of synthesizable design, timing constraints and exceptions.
• Track record of multiple tapeouts (experience with at least 8 tapeouts preferred).
• Experience with industry-standard EDA tools from Synopsys, Cadence, Mentor/Siemens for scan, Lbist insertion and ATPG; TetraMAX experience is a strong plus.
• Attention to detail, strong analytical skills, and effective written and verbal cross-functional communication.
• Ability to debug test failures, modify RTL for scan, and reduce ATE tester time through pattern optimization.

Nice-to-have:

• Mixed-signal experience.
• Exposure to automotive test requirements and ASIL processes.

Education Requirements

BSEE required; MSEE preferred. Typical experience profile specified in the posting: MSEE plus approximately 12+ years, or BSEE plus approximately 15+ years of relevant digital design and DFT implementation experience.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.