Principal Digital Design Engineer (ASIC)

Job Title

Principal Digital Design Engineer (ASIC)

Role Summary

The Principal Digital Design Engineer will define architecture and lead RTL and system-level design for complex ASIC/SoC projects. The role partners with architects, analog designers, verification, physical design, firmware, and product teams to deliver tapeouts and silicon-validated solutions.

Reports as a technical authority, sets technical direction for digital subsystems, and mentors engineering staff.

Experience Level

Senior level. Requires 10+ years of experience in digital ASIC/SoC design; 12+ years preferred.

Responsibilities

Primary responsibilities of the role include:

• Define architecture, micro-architecture, and RTL for complex digital blocks and subsystems (signal processing, control, processor subsystems) for mixed-signal ICs.
• Develop and maintain system-level models (SystemVerilog, MATLAB) to analyze architectural trade-offs and hardware/software partitioning.
• Perform RTL coding in Verilog/SystemVerilog, synthesis, lint/CDC analysis, and drive designs to timing closure and area/power targets.
• Lead design reviews, contribute to specifications, and ensure alignment with project goals and constraints.
• Collaborate across functions (DV, PD, systems, analog, firmware) during architecture, design, evaluation, and release phases.
• Develop and execute verification plans with DV, including functional coverage and support for simulation/debug.
• Contribute to integration tasks: interface definition, constraint development, and support for physical implementation and DFT modes.
• Perform silicon lab evaluation and debug; develop Python-based tests for evaluation platforms.
• Analyze and resolve design, timing, and functional issues across the digital development flow.
• Mentor and guide junior engineers; produce and maintain clear design documentation and user guides.

Requirements

Must-have technical skills and experience. Preferred items are listed separately.

• 10+ years experience in digital design for ASIC/SoC with a track record of successful tapeouts.
• Expertise in RTL design using SystemVerilog and Verilog; strong experience with logic synthesis and implementation flows.
• Proven experience with digital verification methodologies and collaboration with DV teams; working knowledge of Cadence tool flows.
• Experience with timing analysis, constraints, lint, CDC, and driving timing closure.
• Modeling and scripting experience (MATLAB, TCL, Python) for design automation and test development.
• Experience supporting physical implementation and DFT; ability to work with physical design and layout teams.
• Demonstrated ability to lead technical projects or major design subsystems and to communicate technical decisions clearly in cross-functional settings.
• Willingness to travel up to 10% for collaboration and lab work.

Preferred / nice-to-have:

• Familiarity with UVM or similar verification frameworks.
• Experience with high-speed interfaces, high-speed signal processing, and low-power digital design.
• Prior mentorship or formal technical leadership experience.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field — or equivalent practical experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.