Principal Digital Design Engineer

Role Summary

The Principal Digital Design Engineer will lead the design of advanced System-on-Chip (SoC) technologies in Santa Clara, California. This individual will play a crucial role in developing next-generation solutions for AI datacenter switch processors, working closely with cross-functional teams to ensure high performance and efficiency.

Experience Level

This position requires a seasoned professional with a Bachelor’s degree in Computer Science, Electrical Engineering, or a related field and 10-15 years of industry experience, or a Master’s/PhD with 5-10 years of experience in digital IC design.

Responsibilities

• Lead the micro-architecture design of high-performance SoC, focusing on key IP blocks such as Ethernet MAC, PCS, and packet processing.
• Collaborate with architects and verification engineers to design, validate, and optimize timing-critical systems.
• Master all stages of the SoC front-end design flow, ensuring timing closure and power optimization.

Requirements

Candidates must possess extensive experience in System-on-Chip architecture, with a solid background in Verilog RTL creation and optimization. Proficiency in scripting languages, particularly Perl and Python, is essential for improving workflow efficiency.

Education Requirements

A Bachelor’s degree in Computer Science, Electrical Engineering, or a related field is required, with a strong preference for candidates holding a Master’s or Doctorate in the same disciplines.