Principal DFT Engineer

Role Summary

The position involves working as a Senior DFT Engineer with extensive experience in SoC DFT implementation and verification, including key aspects such as scan architectures, JTAG, memory BIST, ATPG, and LBIST.

Experience Level

Candidates should have at least 10 years of experience in the semiconductor industry, with a strong focus on DFT methodologies.

Responsibilities

• Implement and verify scan architectures and JTAG protocols.
• Conduct memory Built-In Self-Test (BIST) and Automatic Test Pattern Generation (ATPG).
• Involve in insertion of scan chains and debug tasks related to simulation failures.
• Utilize Mentor DFT tools and Cadence tools for successful project execution.
• Ensure thorough coverage analysis and timing simulations.
• Collaborate effectively with cross-functional teams to drive project goals.

Requirements

Candidates must possess a BE/ME/B.Tech/M.Tech with a first-class degree from reputed institutions and at least 5 years of industry experience in relevant roles. Proficiency in Verilog/VHDL RTL coding, along with hands-on experience directly related to scan insertion and DFT methodologies, is essential. Ideal candidates should demonstrate strong problem-solving abilities, effective communication skills, and be highly motivated and detail-oriented.

Education Requirements

A Bachelor's or Master's degree in Engineering (BE/ME/B.Tech/M.Tech) is required, with a focus on disciplines relevant to electronics or semiconductor design.