Principal DFT Engineer

Job Title

Principal DFT Engineer

Role Summary

The Principal Digital DFT Engineer will architect, implement, and verify DFT solutions for complex digital ASICs and SoCs, owning DFT flows from design through production. The role requires hands-on execution with EDA tools, close collaboration with RTL and physical design teams, and responsibility for manufacturability and test cost reduction.

Position is based in Bangalore; occasional travel (~10%) is required.

Experience Level

Senior — Principal level. Expect 10+ years of hands-on DFT experience in digital ASIC/SoC development.

Responsibilities

Primary responsibilities include technical ownership of DFT architecture, implementation, validation, and production support.

• Define and implement DFT architecture: scan insertion, ATPG, boundary scan, MBIST/logic BIST, JTAG, and test compression.
• Execute DFT flows using EDA tools for scan synthesis, test pattern generation, and fault simulation.
• Create and validate test plans targeting stuck-at, transition, and critical path faults.
• Integrate DFT with RTL and physical design teams; resolve trade-offs impacting fault coverage, PPA, and manufacturability.
• Optimize test modes and manufacturability; debug silicon failures from bring-up through production ramp.
• Develop low-overhead test structures and warranty/test schemes for new and legacy IP.
• Analyze and resolve DFT issues in simulation, emulation, and lab environments using standard test equipment.
• Deliver documentation, implementation scripts (TCL/Python/Perl), and design guidelines for engineering teams.
• Collaborate with ATE test engineers to implement production tests and reduce test cost.
• Mentor and train junior engineers in DFT methodology and tools.

Requirements

Core technical and practical requirements for successful candidates.

Must-have:

• 10+ years of hands-on DFT experience for digital ASIC/SoC development with multiple tapeouts for large designs.
• Expertise in DFT flows: scan, ATPG, MBIST, BIST, JTAG, boundary scan, and fault simulation.
• Proficiency with EDA DFT tools such as Synopsys DFT Compiler, Tessent, Cadence Modus, or equivalent.
• Scripting skills for automation and reporting (TCL, Python, Perl).
• Solid knowledge of RTL design, synthesis, timing, and SoC architecture constraints.
• Proven ability to debug complex DFT and test-mode issues at lab and production levels.
• Ability to produce technical documentation and mentor other engineers.

Nice-to-have / Preferred:

• DFT experience at advanced process nodes (≤ 7nm), 2.5D/3D packaging, or high-speed IP.
• Production ATE pattern development and test data evaluation experience.
• Familiarity with safety (ISO 26262) or security-related DFT requirements.
• Experience with memory BIST (SRAM/DRAM) and custom macro testing.

Education Requirements

Bachelor’s or Master’s degree in Electrical, Electronics, VLSI Engineering or a related technical field, or equivalent practical experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.