Principal Design Verification Engineer

Job Title

Principal Design Verification Engineer

Role Summary

Join the Infrastructure Processor Business Unit verifying multi-core SoCs and IP (OCTEON family) used in AI/ML, networking, compute, automotive and baseband applications. The role focuses on planning and executing functional verification to ensure designs meet customer and industry requirements.

Work involves architecting verification environments, developing tests and reference models, debugging failures, and collaborating with designers and cross-functional teams to close coverage and quality goals.

Experience Level

Senior — typically requires extensive verification experience; see Education Requirements for degree-specific experience guidance.

Responsibilities

Core responsibilities include building and running verification environments, driving coverage closure, and resolving functional issues.

• Architect and implement functional verification environments using SystemVerilog and UVM.
• Develop verification test plans, create tests using constrained-random techniques, and perform coverage analysis.
• Build reference models, bus-functional monitors, and drivers; tune environments to meet coverage goals.
• Debug failures, analyze root causes, and work with designers to resolve functional and integration issues.
• Develop and maintain tools and infrastructure to streamline verification of multicore SoCs.
• Participate in code and functional coverage analysis and closure activities.

Requirements

Must-have technical skills and experience:

• Strong experience developing complex/random verification environments using SystemVerilog and UVM.
• Proven ability to write and execute detailed verification test plans and achieve coverage goals.
• Proficiency with scripting (Python or Perl) and use of EDA verification tools, bug tracking, and regression flows.
• Solid object-oriented design and implementation skills.
• Experience debugging RTL-level failures and collaborating with design teams to drive fixes.

Preferred / nice-to-have:

• Hands-on verification experience with processor subsystems (ARM), memory, NoC, networking, caches.
• Familiarity with protocols such as AMBA, PCIe, Ethernet, I2C, SPI, UART.
• Working knowledge of C/C++ for modeling and processor-resident code.
• Post-silicon validation/debug experience and gate-level simulation familiarity.
• Strong communication, analysis, and multitasking skills in fast-paced projects.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or related field with 10–15 years of relevant professional experience; or Master's degree and/or PhD in Computer Science, Electrical Engineering, or related field with 5–10 years of relevant experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.