Principal Design Verification Engineer
RenesasRole Summary
The Principal Design Verification Engineer will lead and contribute to the verification of complex MCU / SoC designs, ensuring that functionality, performance, and quality meet project specifications.
Experience Level
Senior level with typically 12+ years of experience in design verification or related MCU / SoC development roles.
Responsibilities
The responsibilities include:
- Define and own end-to-end verification strategy for MCU / SoC.
- Develop verification plans based on specifications.
- Architect and enhance verification environments using SystemVerilog and UVM.
- Lead debugging and root-cause analysis of functional issues.
- Drive continuous improvement of verification methodologies.
- Mentor and coach verification engineers.
Requirements
Must-have qualifications include:
- Strong experience in MCU / SoC design verification.
- Proficiency in SystemVerilog, UVM, and SVA.
- Strong debugging capabilities at RTL and simulation levels.
- Experience in leading verification activities through silicon sign-off.
Preferred qualifications include:
- Experience with formal verification and low-power verification.
- Exposure to functional safety or security-related verification.
- Prior experience as verification lead for MCU / SoC projects.
Education Requirements
Not specified.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
