Principal Design Engineer

Role Summary

The Principal Design Engineer role at Cadence Design Systems focuses on leading design verification efforts for complex electronic designs, ensuring thorough testing and validation of products before they are released.

Experience Level

Candidates should possess 7+ years of relevant experience in design and verification engineering, showcasing a strong background in functional verification fundamentals.

Responsibilities

• Lead design verification projects from initial concept through to verification closure.
• Generate environment plans and test plans to ensure comprehensive verification coverage.
• Develop robust functional verification environments using System Verilog and UVM coding standards.
• Verify complex design specifications, with a specific focus on memory IP (DDR/HBM/GDDR) where applicable.

Requirements

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/VLSI.
• Extensive experience in design verification using System Verilog and UVM.
• Strong hands-on skills in functional verification environment development.
• Prior experience in IP verification will be considered an advantage.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics/VLSI Engineering.