Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Technical lead for digital verification on ASIC/SoC projects, responsible for verification strategy, testbench architecture, and delivery of sign-off quality verification. Works with customers, design architects, and cross-functional teams to drive verification from planning through sign-off.

Experience Level

Senior — 7–10 years of hands-on design verification (DV) experience in semiconductor/ASIC/SoC environments.

Responsibilities

Lead verification planning and execution, mentor engineers, and manage verification metrics and sign-off activities.

• Define verification strategy, methodology (UVM/SystemVerilog), tools, and infrastructure.
• Design scalable, reusable testbench architecture: BFMs, monitors, scoreboards, and checkers.
• Translate architectural specifications into verification features and corner-case tests.
• Lead DV execution for small to mid-sized customer ASIC projects and act as technical customer contact.
• Develop complex test cases and constrained-random sequences to achieve functional coverage targets.
• Drive root-cause analysis and debug of complex design issues in collaboration with design engineers.
• Use formal verification tools to prove properties or find deep bugs beyond simulation.
• Monitor coverage metrics, oversee gate-level (GLS) simulations, and define verification sign-off criteria.

Requirements

Key skills and experience required to perform the role.

• Must-have: 7–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies.
• Must-have: Deep expertise in SystemVerilog and UVM.
• Must-have: Strong understanding of digital design fundamentals: RTL, timing, clocking, and resets.
• Must-have: Experience with industry simulators such as Xcelium, VCS, or Questa.
• Must-have: Proficiency in coverage-driven verification (functional, code, toggle) and coverage analysis.
• Must-have: Hands-on experience with formal verification tools and flows.
• Must-have: Experience with common bus/protocol interfaces (AXI, AHB, APB, PCIe, DDR or similar) and strong waveform debug skills (e.g., Verisium, SimVision).
• Nice-to-have: Familiarity with low-power verification (UPF/CPF) and power-aware GLS simulation.

Education Requirements

B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or a related field.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.