Principal Design Engineer

Job Title

Principal Analog Design Engineer (SERDES)

Role Summary

Technical lead on the PMA design team within a SERDES product group located in Cork, Ireland. Responsible for architecture and analog/mixed-signal circuit design for high-speed SERDES products up to and beyond 112 Gbps on advanced CMOS nodes.

Role includes hands-on circuit design, verification to customer specifications, coordination with physical design and global teams, and technical leadership of the analog design effort.

Experience Level

Senior — requires at least 7 years of experience in CMOS SERDES or high-speed I/O IC design and development.

Responsibilities

Key responsibilities include:

• Design high-speed SERDES products at data rates up to and exceeding 112 Gbps on leading-edge process nodes (example: 5nm FinFET CMOS).
• Develop analog/mixed-signal IC circuit blocks from concept/specification through final verification against customer requirements.
• Collaborate closely with Physical Design Engineers on IC circuit blocks and PMA sections.
• Provide technical leadership on circuit design and SERDES architecture within the team.
• Coordinate and work with global teams across different time zones (US West Coast and East Coast).
• Participate in silicon lab evaluation and support test activities as required.
• Travel as required: >5%.

Requirements

Must-have skills and qualifications:

• Minimum 7 years experience in CMOS SERDES or high-speed I/O IC design and development.
• Working knowledge of common SERDES standards and their electrical requirements.
• Thorough understanding of jitter and signal equalization techniques.
• Proven design experience with SERDES circuit blocks such as Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low-jitter PLL, High-speed Clock Distribution, Bias and Bandgap, and Voltage Regulators.
• Strong problem-solving skills, solid analog aptitude, and effective verbal/written communication; able to work cooperatively in a team.
• Ability to provide technical leadership and collaborate across geographically distributed teams.

Nice-to-have:

• Experience with Cadence tools and designs operating >10 Gbps and in <40 nm technologies.
• Lab test and silicon evaluation experience.
• Interest in publishing or presenting at conferences (e.g., ISSCC, JSSC).

Education Requirements

Listing on the posting: BEng, MEng, or PhD required/qualified. No specific fields of study were specified in the source.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.