Principal ASIC Physical Design Engineer
SynopsysJob Title
Principal ASIC Physical Design Engineer
Role Summary
Lead physical implementation and signoff for complex ASIC projects within the ASIC Physical Design team. Drive floorplanning, placement, timing closure, power optimization, and tapeout readiness across advanced process nodes.
Work cross-functionally with RTL designers, IP teams, verification, DFT, and manufacturing to meet schedule, quality, and performance targets.
Experience Level
Senior (Principal). Typical guidance: senior/principal engineer level with substantial hands-on ASIC physical design experience; often 10+ years in industry.
Responsibilities
The role is accountable for technical leadership, delivering physical design milestones, and improving design flows.
- Lead physical design tasks: floorplanning, placement, clock tree synthesis, routing, and optimization to meet timing, power, and area targets.
- Perform static timing analysis, congestion analysis, and signoff-quality verification; coordinate ECOs and timing closure activities.
- Drive power analysis and optimizations including clock gating, power intent implementation, and low-power flows.
- Collaborate with RTL/IP/DFT/verification teams to resolve implementation issues and ensure design-for-manufacturability.
- Mentor and provide technical guidance to junior engineers; define best practices and improve physical design methodologies.
- Prepare and review tapeout deliverables and ensure compliance with IP and foundry requirements.
- Evaluate and adopt EDA tool flows and automation to increase productivity and quality.
Requirements
Must-have technical skills and experience required for the role; nice-to-have items listed separately.
- Must-have: Extensive hands-on ASIC physical design experience across full implementation flow (floorplan, place & route, timing closure, signoff).
- Proficiency in static timing analysis, power analysis, and physical verification flows.
- Scripting skills for automation (Tcl, Python, Perl, or equivalent).
- Experience working with advanced process nodes and managing tapeout schedules.
- Strong collaboration and communication skills to coordinate cross-functional teams and deliver against milestones.
- Nice-to-have: Experience with common EDA tool flows and commercial physical design tools; familiarity with DFT, LVS/DRC flows, and foundry signoff processes.
Education Requirements
Not specified.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
