Principal ASIC Physical Design Engineer

Role Summary

This role involves leading the ASIC physical design implementation of test chips for various protocols, including DDR, HBM, and UCIe. The engineer will oversee the physical design team and ensure successful project execution through effective leadership, technical expertise, and collaboration with cross-functional teams.

Experience Level

We are seeking seasoned professionals with a minimum of 12 years of demonstrated experience in ASIC physical design, particularly in managing complex SoC or test chip implementations at advanced process nodes.

Responsibilities

• Lead the physical design implementation of test chips, including integration of IP blocks and custom logic.
• Oversee the physical design process, from floor planning to GDSII, ensuring design convergence on area, power, and performance.
• Manage a team of engineers, allocating resources and scheduling tasks to meet project deadlines.
• Conduct static timing analysis (STA) and resolve physical verification issues, ensuring robust timing signoff.
• Drive tool flow automation to enhance productivity and improve design reliability.
• Prepare necessary documentation required for tape-out processes and engage with foundry portals.

Requirements

Candidates should have an extensive background in the ASIC physical design flow and proven leadership skills in high-pressure environments. Candidates must demonstrate proficiency with CAD tools and possess strong analytical and communication skills.

Education Requirements

A degree in Electrical Engineering, Computer Engineering, or a related field is required; advanced degrees are preferred.