Principal ASIC Physical Design Engineer
SynopsysJob Title
Principal ASIC Physical Design Engineer
Role Summary
Lead and execute advanced-node ASIC physical design for high-frequency SoCs and IP, focusing on timing closure, clock-tree synthesis, floorplanning, placement, routing, and power optimization. Work hands-on in a cross-site engineering team to deliver silicon-proven designs and mentor junior engineers.
The role is engineering-focused and includes collaboration with teams in Bengaluru and the US to drive robust tapeouts and improve physical design flows.
Experience Level
Senior — typically 10+ years of hands-on ASIC physical design experience at advanced process nodes (10nm, 7nm, 6nm or below).
Responsibilities
Primary responsibilities include implementing and optimizing physical design flows, achieving timing closure on high-frequency designs, and integrating complex IP. Expect hands-on execution and mentoring duties.
- Implement and integrate physical design at advanced nodes using industry tools.
- Drive timing closure for high-frequency designs (above 4GHz): constraint management, analysis, and optimization.
- Design and optimize clock tree synthesis, skew balancing, and clock distribution for complex SoCs and IPs.
- Integrate mixed-signal hard macros and IP, addressing floorplan and interface challenges.
- Develop and maintain automation scripts (Tcl, Perl, Python) to improve productivity and flows.
- Mentor junior engineers, review floorplans and layouts, and raise team technical capability.
- Support and refine methodologies for floorplanning, placement, routing, and power optimization.
Requirements
Key technical requirements and preferred skills. Degree information is listed separately under Education Requirements.
Must-have:- 10+ years of hands-on ASIC physical design experience at 10nm, 7nm, 6nm or below.
- Deep proficiency with Synopsys ICC2, PrimeTime, StarRC, and similar physical-design and signoff tools.
- Proven success in timing closure for high-frequency designs (4GHz+), including constraint development and analysis.
- Experience integrating controller IPs and mixed-signal hard macros into SoC floorplans.
- Proficiency in scripting for automation (Tcl, Perl, Python).
- Strong debugging and root-cause analysis skills for complex integration issues.
- Experience developing or improving physical-design methodologies and automation frameworks.
- Prior mentorship or leadership experience within multi-site design teams.
Education Requirements
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or a related technical field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, United States
Developer of electronic design automation (EDA) software and semiconductor IP, offering tools and services for silicon design, verification, simulation, and analysis to enable advanced AI-powered products and complex system-on-chip development.
