Principal ASIC Design Engineer (Silicon Engineering)

Role Overview

The Principal ASIC Design Engineer at SpaceX plays a critical role in the development of the next-generation FPGAs and ASICs used in both space and ground infrastructures globally. This position involves collaboration with cross-disciplinary teams to design and innovate solutions that enhance the Starlink network.

Position Summary

In this role, you will be responsible for designing digital ASICs and FPGAs specifically for Starlink projects. Your expertise will contribute to building a system that provides reliable internet access in challenging environments, thereby expanding connectivity possibilities.

Experience Level

This position requires a senior-level engineer with at least 10 years of relevant experience in RTL implementation and FPGA/ASIC development.

Key Responsibilities

• Design digital ASICs and FPGAs for Starlink projects.
• Evaluate architectural trade-offs based on features, performance, and system limitations.
• Define micro-architecture and implement RTL in Verilog/System Verilog.
• Collaborate with verification teams to ensure comprehensive design testing.
• Provide timing constraints and support physical implementation teams.
• Contribute to silicon bring-up and validation efforts.

Essential Requirements

Candidates must have a Bachelor’s degree in electrical engineering, computer engineering, or computer science, coupled with over 10 years of substantial experience in ASIC and FPGA development.

Preferred Qualifications

Preferred candidates will have experience in solving clock domain crossings and power optimization, developing complex ASICs, and working with embedded processors, as well as scripting skills (e.g., Python, TCL) and familiarity with EDA tools. A collaborative mindset and a proactive approach to challenges are essential.

Education Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science.