Principal ASIC Design Engineer

Role Summary

The Principal ASIC Design Engineer will develop ASICs and FPGAs as part of the engineering team at SpaceX. The focus will be on enhancing Starlink technologies to ensure fast, reliable broadband connectivity worldwide. This role requires collaboration with cross-disciplinary teams to advance the designs essential for operational success.

Experience Level

This position requires a minimum of 10 years in RTL implementation and/or FPGA/ASIC development.

Responsibilities

• Design and implement digital ASICs and/or FPGAs for Starlink projects.
• Evaluate architectural trade-offs concerning features and performance.
• Define micro-architecture and implement RTL in Verilog/System Verilog.
• Collaborate with verification teams to ensure comprehensive coverage and verification of designs.
• Provide timing constraints and support physical implementation teams.
• Participate in silicon bring-up and validation processes.

Requirements

• Must possess a Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of relevant experience in RTL implementation or FPGA/ASIC development.

Education Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science is required.