Power & Performance Engineer - Platform Architecture

Job Title

Power & Performance Engineer - Platform Architecture

Role Summary

The engineer will deprocess, image, and analyze silicon to extract technical intelligence on process technology, circuit design choices, memory architectures, and logic implementation efficiency. Work supports Platform Architecture and informs Apple's SoC roadmap, power and performance tradeoffs, and integration decisions.

This role partners with silicon design teams, failure analysis labs, and external vendors to plan and execute physical analysis campaigns and communicate quantitative findings.

Experience Level

Senior level. Preferred ~10+ years industry experience (experience requirement: senior/principal engineer).

Responsibilities

The main responsibilities focus on planning and executing silicon physical-analysis campaigns and translating physical measurements into actionable design intelligence.

• Plan and perform layer-by-layer deprocessing and imaging of SoCs (chemical etch, mechanical polish, pFIB).
• Acquire and analyze SEM/TEM/FIB images and EDS data to characterize process and design implementation.
• Identify and interpret logic and memory structures from physical images, including SRAM bitcells and cache hierarchy estimation.
• Estimate quantitative metrics such as area, density, logic utilization, and silicon efficiency.
• Coordinate with failure analysis labs and external vendors for chip extraction, sample preparation, and imaging workflows.
• Produce clear technical reports and present findings to cross-functional silicon design teams to inform roadmap and design decisions.
• Develop basic image-analysis and measurement scripts and tools to support quantitative assessments.

Requirements

Must-have technical skills and experience required to perform the role; preferred items indicate stronger candidates.

• Must-have: Experience in semiconductor physical analysis including layer-by-layer deprocessing (chemical etch, mechanical polish, pFIB), SEM/TEM/FIB imaging, or EDS characterization of SoCs.
• Must-have: Practical experience producing and communicating analysis results to engineering teams.
• Nice-to-have: Familiarity with silicon implementation and design (floorplans, standard cell libraries, FinFlex configurations, fin counts, metal-stack identification, foundry/process differentiation).
• Nice-to-have: Ability to identify memory and logic library types from physical images and perform SRAM bitcell characterization and cache hierarchy estimation.
• Nice-to-have: Experience coordinating with failure analysis labs and external vendors to execute deprocessing campaigns.
• Nice-to-have: Basic image-analysis, measurement, and scripting experience (Python, shell) for quantitative area and density estimation.
• Nice-to-have: Industry engagement (conferences or publications) and demonstrated interest in semiconductor and consumer-electronics trends.

Education Requirements

Minimum: BS in Electrical Engineering, Materials Science, Physics, or a similar engineering degree, or equivalent practical work experience. Preferred: MS or PhD in EE, Materials Science, Physics, or similar engineering field.

About the Company

Company: Apple

Headquarters: Cupertino, California, United States

Apple is a multinational technology company that designs, manufactures, and markets consumer electronics, software, and services — including the iPhone, Mac, iPad, Apple Watch, and operating systems — focused on integrated hardware-software experiences.