Post Silicon Validation Engineer II
Join an IP engineering team responsible for digital and mixed-signal IP (examples: PCIe, Ethernet). The role focuses on post-silicon bring-up, characterization, and validation of high-speed designs in a laboratory environment.
Collaborate with designers and application engineers to develop validation plans, execute experiments, analyze results, and produce technical reports for internal and customer use.
Mid-level β typically requires 1+ years of validation experience in high-speed analog/mixed-signal designs.
Primary responsibilities include hands-on lab validation, test automation, and cross-functional collaboration.
Must-have technical skills and experience.
Nice-to-have: experience with protocol IP (PCIe, Ethernet) and customer-facing demo/support experience.
B.S. or M.S. in Electrical Engineering, Computer Engineering, Engineering Science, or a related engineering discipline.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
