PMTS, Design Verification Lead

Job Title

PMTS, Design Verification Lead

Role Summary

Lead verification strategy, planning, execution, and signoff for next-generation RISC-V based processor IP products. Manage a team of verification engineers to ensure functional correctness, quality, performance, safety, and robustness of processor subsystems and full-chip IP solutions.

Work cross-functionally with architecture, RTL design, emulation/FPGA, software, and validation teams to close coverage, drive verification readiness, and deliver silicon-proven IP to production.

Experience Level

Senior — typically 12+ years of relevant industry experience in ASIC/SoC/processor verification and proven technical/people leadership.

Responsibilities

Accountable for verification strategy, execution, and program-level signoff.

• Define and own verification strategy, signoff criteria, coverage goals, and verification milestones for processor IP and subsystems.
• Plan verification activities, allocate resources, track progress, and present status and risks to executive leadership.
• Architect scalable verification environments using SystemVerilog, UVM, assertions, and constrained-random techniques; define reusable infrastructure.
• Drive verification readiness reviews, risk assessments, bug triage, root-cause analysis, and closure.
• Oversee development of directed, random, compliance, and software-driven test suites and ensure coverage closure.
• Coordinate adoption of formal verification, emulation, FPGA prototyping, and hardware/software co-verification where appropriate.
• Mentor and provide technical direction to verification engineers across multiple projects and sites.
• Collaborate with architecture, design, validation, and software teams to ensure comprehensive verification coverage and product quality.

Requirements

Must-have technical skills and experience to perform the role.

• Proven leadership running verification teams for complex CPU, MCU, DSP, or processor IP products.
• Deep expertise in SystemVerilog, UVM, assertions (SVA), functional coverage, and constrained-random verification.
• Strong understanding of processor architecture and microarchitecture (cores, MMUs, caches, interrupts, debug, security).
• Experience with RISC-V, ARM, or equivalent ISA verification and architectural validation.
• Experience with simulation, emulation, regression infrastructures, and coverage-driven verification.
• Proven ability to define signoff methodologies, quality metrics, and verification processes that scale across product families.
• Excellent project leadership, communication, and cross-functional collaboration skills.

Nice-to-have:

• Experience with vector extensions, DSP architectures, functional safety or cybersecurity standards (e.g. ISO 26262, ISO 21434).
• Practical experience with formal verification, emulation platforms, FPGA prototyping, and software-driven/performance verification.
• Prior leadership of globally distributed teams and building verification environments from scratch.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is specified in the source posting.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.