Place and Route Design Automation Engineer

Job Title

Place and Route Design Automation Engineer

Role Summary

Member of the Design Methodology and Automation team responsible for development and support of automated place-and-route (P&R) tools, flows, and methodologies for next-generation FPGA silicon. Collaborate with physical design, CAD, RTL, synthesis, and cross-functional teams to improve quality of results (QoR), runtime, and overall flow robustness.

Experience Level

Mid-level — minimum 3+ years of relevant industry experience in semiconductor physical design or design automation.

Responsibilities

Primary responsibilities include developing, maintaining, and supporting P&R automation flows and providing end-user support.

• Develop and enhance P&R tools, flows, and automation utilities to improve usability, efficiency, and scalability.
• Maintain and improve existing P&R automation infrastructure and methodologies for FPGA silicon development.
• Provide end-user support: debug flow and tool issues, promote best practices, and document procedures.
• Work on QoR improvements including timing, power, congestion, density, and design closure.
• Evaluate and test new P&R tool capabilities and methodologies and implement practical optimizations.
• Identify design or flow bottlenecks and implement fixes or process improvements.
• Collaborate with multi-geo and cross-functional teams (physical design, RTL, synthesis, CAD) to ensure robust end-to-end flow support.
• Document methodologies, flow updates, and usage guidelines.

Requirements

Must-have technical skills and hands-on experience.

• Hands-on experience with Place & Route (P&R), physical design, or design automation in FPGA or ASIC environments for 3+ years.
• Experience using industry-standard EDA P&R tool suites (e.g., Synopsys, Cadence) in production design environments.
• Strong scripting and coding skills in Tcl, Perl, and Python for automation and tool integration.
• Proficiency in Unix/Linux development environments.
• Applied knowledge of physical design fundamentals: floorplanning, placement, clocking, routing, and static timing analysis (STA).
• Experience debugging and resolving tool, flow, or design issues in a collaborative engineering environment.
• Experience collaborating with cross-functional and multi-geo teams to support design execution.
• Ability to evaluate tool capabilities, test new methodologies, and implement QoR and runtime optimizations.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is specified, with a requirement of 3+ years of industry experience in semiconductor design or design automation. No alternative "equivalent experience" language was provided in the posting.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.