Physical Verification Engineer

Job Title

Physical Verification Engineer

Role Summary

Provide technical support and verification methodology leadership for Intel Foundry customers working on advanced CMOS process nodes. Focus areas include layout verification, parasitic extraction, verification flow optimization, and customer-facing technical guidance to enable successful tape-outs.

Position sits in Intel Foundry Services' Aerospace, Defense & Government (ADG) domain and interfaces with customers, IP providers, EDA vendors, and internal engineering teams.

Experience Level

Mid-level — typically requires 3+ years of relevant experience with advanced CMOS processes and verification tools.

Responsibilities

Primary responsibilities include technical support, methodology development, and customer engagement.

• Provide technical support on layout verification and parasitic extraction to foundry customers.
• Collaborate with internal teams, customer design teams, IP providers, and EDA vendors to resolve verification and extraction issues.
• Resolve complex verification challenges across advanced CMOS processes (22nm and below) to enable successful customer design implementations.
• Develop application notes, documentation, best-practice guidelines, and training materials for customers and internal teams.
• Drive quality improvements in design kits, rule decks, and verification documentation.
• Lead optimization of physical verification flows and provide technical direction on DRC, LVS, ERC, and PERC methodologies.
• Deliver customer-facing technical support and maintain high customer satisfaction through timely, expert guidance.

Requirements

Must-have qualifications are listed first; preferred skills follow.

• Must-have: US Citizenship required and ability to obtain a U.S. Government security clearance.
• Must-have: 3+ years of experience with advanced CMOS processes (22nm and below).
• Must-have: 3+ years combined experience using layout verification and parasitic extraction EDA tools.
• Must-have: 3+ years experience with scripting (Python, Perl, Tcl, and/or shell scripting).
• Preferred: Active U.S. Government security clearance (minimum Secret).
• Preferred: Hands-on experience in LVS, DRC, ERC, and PERC implementations.
• Preferred: Experience with parasitic extraction tools such as StarRC, Cadence Quantus, or Synopsys xACT.
• Preferred: Experience with major layout/ECO/verification tools and flows (ICV, Calibre, Pegasus) and rule-deck coding for those tools.
• Preferred: Experience providing technical direction to engineering teams and prior customer-facing support experience.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field is required. A postgraduate degree in those fields is preferred. The posting allows the minimum qualifications to be satisfied through a combination of industry experience, internships, coursework, or research (equivalent practical experience).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.