Physical Design Timing Engineer

Job Title

Physical Design Timing Engineer

Role Summary

Responsible for timing analysis, optimization, and clock-network design for DDR PHY IP and related SoC blocks. The role works across architecture, logic, and physical design teams to ensure timing closure, robustness, and efficient power/performance trade-offs.

Part of a central engineering team delivering IP, tools, and methodologies that support product enablement and custom silicon development.

Experience Level

Level: Senior. Typical experience expected: multi-year practical experience in physical-design timing (guidance from posting suggests senior-level experience).

Responsibilities

Primary duties include timing signoff, clock-network design, and methodology development to meet performance and reliability targets.

• Perform chip/block-level static timing analysis and optimize designs to resolve timing violations.
• Generate and validate timing constraints and perform timing rollups for physical design flows.
• Design and optimize clock networks for power and performance while meeting product requirements.
• Define PVT conditions for timing analysis aligned with operating conditions and binning plans.
• Collaborate with architecture, clock, logic, and backend teams on integration, clock balance, routing, partitioning, and power delivery.
• Analyze noise glitches and signal integrity issues to ensure design robustness.
• Develop and refine timing models, tools, flows, and methodologies to streamline physical implementation.

Requirements

Must-have technical skills and experience; preferred items noted separately.

• Must-have: Proficiency with static timing analysis tools and timing methodologies.
• Must-have: Expertise in clock design, timing budgeting, and constraint adaptation.
• Must-have: Practical experience scripting (TCL) to support flows and automation.
• Must-have: Strong knowledge of physical-design fundamentals including extraction, noise/glitch analysis, and signal integrity.
• Must-have: Familiarity with FEM/PV scaling methods and library characterization.
• Preferred: Prior involvement in memory/PHY design and cross-functional collaboration across architecture and implementation teams.
• Preferred: Experience developing tools, methodologies, or workflows that improve physical-design efficiency.
• Preferred: Demonstrated problem-solving under tight schedules and effective communication in cross-functional teams.

Education Requirements

Degree and experience combinations specified in the posting: Bachelor's degree with 6+ years of relevant experience, Master's degree with 4+ years, or PhD with 2+ years in Electrical Engineering, Computer Engineering, or a related technical field in physical-design timing engineering or SoC development. The posting also allows equivalent practical experience obtained via industry work, internships, or research.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.