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Physical Design Engineer with RTL Design Background

Texas Instruments
May 27, 2026
Full-time
On-site
Bengaluru, Karnataka, India
Physical Design Jobs, Level - Mid-Career

Job Title

Physical Design Engineer with RTL Design Background

Role Summary

Responsible for taking RTL through the full physical design flow—synthesis, floorplanning, placement, CTS, routing, timing closure, power optimization and physical verification—for complex mixed-signal SoC/ASIC blocks (audio-focused).

Work closely with RTL, verification and architecture teams and provide EDA flow automation and sign-off support to achieve tape-out quality designs.

Experience Level

Mid-level — 2–5 years of industry experience in physical design for ASIC/SoC.

Responsibilities

The core responsibilities include:

  • Execute RTL-to-GDSII physical design flow for complex SoC/ASIC blocks.
  • Perform logic synthesis, floorplanning, placement, clock tree synthesis (CTS), and routing.
  • Develop and maintain design constraints; support static timing analysis (STA) across multiple corners and modes.
  • Optimize designs for area, power and performance (PPA) at block and chip level.
  • Perform physical verification and sign-off checks including DRC, LVS, antenna checks, IR-drop and EM analysis.
  • Provide EDA flow automation and scripting support (Tcl/Perl/Python).
  • Collaborate with RTL, verification and architecture teams to resolve implementation issues and participate in design reviews and documentation for sign-off.

Requirements

Must-have skills and experience; preferred items listed separately.

  • 2–5 years of hands-on physical design experience for ASIC/SoC (RTL-to-GDSII flow).
  • Strong knowledge of CMOS and digital VLSI fundamentals and timing analysis.
  • Proficiency with EDA tools (Cadence Innovus, Tempus, Voltus or equivalent).
  • Experience with signoff-level checks: DRC, LVS, IR-drop, EM and noise analysis.
  • Strong scripting skills for flow automation (Tcl, Perl, or Python).
  • Expertise in floorplanning, placement, CTS, routing, timing closure and PPA optimization.
  • Hands-on experience with Cadence simulation tools and debugging physical design issues.
  • Effective communication, collaboration and problem-solving skills; ability to work to deadlines.

Nice-to-have / preferred:

  • Knowledge of audio signal chain, I2C, ASI/TDM, memory architecture and FPGA integration.
  • Hands-on RTL coding experience and familiarity with digital quality checks (Lint/CDC/RDC).

Education Requirements

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI or a related technical field (Bachelor's or Master's degree specified).


About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.

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Date Posted: 2026-05-26