Physical Design Engineer for Core IP

Job Title

Physical Design Engineer for Core IP

Role Summary

Member of Intel's CPU development team responsible for physical implementation and signoff of CPU core intellectual property used across client, server, IoT and AI processors. Work spans RTL-to-GDS implementation, verification/signoff, and optimization for power, frequency and area.

Experience Level

Mid-level. Candidates are expected to have multiple years of relevant ASIC/CPU physical-design experience, typically 2–5+ years working on synthesis and physical design flows.

Responsibilities

Key day-to-day responsibilities include implementing CPU blocks and ensuring they meet functional, timing and reliability goals.

• Perform RTL-to-GDS physical implementation: synthesis, floorplanning, place & route, clock tree synthesis, routing and signoff database creation.
• Execute static timing analysis, power and noise analysis, power/clock distribution and reliability verification.
• Perform verification and signoff activities: formal equivalence, timing signoff, electrical rule checks, DRC/LVS, noise and electromigration analysis.
• Analyze results and recommend design or microarchitecture changes in collaboration with logic, circuit, architecture and design-automation teams.
• Work with EDA vendors to improve tool capabilities and automation for high-speed, low-power CPU design.
• Optimize CPU blocks for product-level metrics (power, frequency, area) and contribute to physical-design methodology improvements.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Minimum experience in synthesis of a digital logic block or partition (practical expectation: 2+ years in synthesis-related work).
• Hands-on experience with integrated-circuit EDA tools (Synopsys or Cadence tool flows) covering logic synthesis, place & route, static timing analysis and design closure.
• Experience with PV convergence including static timing and power analysis.
• Chip physical-design verification experience: formal equivalence, timing, electrical-rule checking, DRC/LVS, noise and electromigration checks.
• Scripting proficiency in TCL plus at least one other interpreted language (Python, Perl, Ruby, etc.).
• Nice-to-have: CPU-level timing analysis and optimization; experience generating/maintaining timing constraints; familiarity with Synopsys Fusion Compiler/ICC2/PrimeTime or Cadence Genus/Innovus; expertise in floor-planning, clock distribution and multi-power-domain analysis.

Education Requirements

Posting specifies degree-based minimums: Bachelor's in Computer Engineering, Electrical Engineering, or a related field (with 3+ years relevant experience), or a Master's or higher (with 2+ years relevant experience). The posting also notes that required qualifications may be met through a combination of industry experience, internships, coursework or research (equivalent practical experience).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.