Physical Design Engineer (EM/IR Closure Engineer)

Job Title

Physical Design Engineer (EM/IR Closure Engineer)

Role Summary

The Physical Design Engineer is an individual contributor responsible for block- and subsystem-level EM/IR analysis and reliability closure within established signoff frameworks.

The role works closely with Physical Design, STA, and Methodology teams to deliver implementation, verification, and signoff for IP and SoC designs.

Experience Level

Mid-level. Typical candidates have multiple years of industry experience (minimums vary by degree; see Education Requirements).

Responsibilities

Primary responsibilities include hands-on implementation, analysis, and closure activities at block and subsystem level.

• Execute RTL-to-GDS physical implementation (synthesis, place & route, CTS, floorplanning, power/clock distribution).
• Perform verification and signoff tasks: equivalence, reliability, static/dynamic power integrity, layout and electrical rule checking, timing analysis.
• Conduct EM/IR analysis and close reliability issues for assigned blocks and subsystems.
• Identify, debug, and resolve violations; recommend architectural or implementation changes.
• Optimize designs for power, frequency, and area using industry EDA tools.
• Develop and improve physical design methodologies, automation flows, and processes.
• Define constraints for hierarchical integration and floorplanning; support ECO cycles and closure loops.
• Collaborate with cross-functional teams to meet quality and performance goals.

Requirements

Must-have technical skills, eligibility, and communication requirements. Preferred items listed separately.

• Proficiency in scripting for design flow automation (Python, Tcl, Perl).
• Expertise with static timing analysis and layout verification tools (e.g., Calibre DRC) and physical clock design.
• Hands-on physical design implementation experience for custom IP and SoC using Synopsys or Cadence toolflows.
• Intermediate to advanced English communication skills.
• Must have unrestricted, permanent right to work in Mexico (no visa or immigration sponsorship available).

Preferred:

• Experience with signoff tools such as PrimeTime PX, PrimeRail, RedHawk or equivalent.
• Understanding of power delivery networks, reliability fundamentals, and signoff criteria.
• Experience with EM/IR analysis and closure for advanced nodes (e.g., 3nm or below).
• Familiarity with Physical Design ECO cycles and closure loops.

Education Requirements

Bachelor's (BS) in Electronics Engineering, Computer Engineering, or a related technical field with 3+ years' relevant experience; OR Master's (MS) in a related field with 2+ years' experience; OR PhD in a related field with no experience required. Requirements may be met through a combination of industry experience, internships, coursework, or research.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.