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Physical Design Engineer

NVIDIA
May 17, 2026
Full-time
On-site
Yokne'am Illit, Israel
Physical Design Jobs, Level - Mid-Career

Job Title

Physical Design Engineer

Role Summary

Chiplet Layout owner on NVIDIA Networking's Israel team responsible for physical integration of high-speed IP across chiplets and full-chip assemblies. The role covers floorplanning, implementation, signoff, PD data analysis, automation, and collaboration with partition owners and STA engineers to improve quality of results.

This is an engineering role focused on physical layout, tooling, and methodology for high-speed networking chiplets.

Experience Level

Mid-level. No specific years of experience specified.

Responsibilities

The role requires ownership of chiplet and full-chip physical design tasks from planning to signoff, tool and flow development, data analysis, and cross-team coordination.

  • Own high-speed IP integration across chiplets and partitions.
  • Build chiplet floorplans and implement partition-level BE design from early planning through signoff.
  • Collect, curate, and summarize PD data (timing, congestion, DRC, routing metrics) and produce dashboards or summaries to show trends and regressions.
  • Develop automation, scripts, and lightweight tools using Python and Tcl; create scripts for run setup, log parsing, QoR comparison, and root-cause analysis.
  • Resolve congestion, utilization issues, and DRC hotspots; iteratively optimize to improve quality of results.
  • Work closely with partition owners and Full Chip STA engineers to ensure timely convergence and high quality.
  • Define and implement efficient full-chip and chiplet physical design tools, flows, and methodologies.

Requirements

Must-have technical skills, practical abilities, and team qualities.

  • Proven experience with Linux and scripting; Python preferred, Tcl is a plus.
  • Comfort working with data: parsing text reports, using pandas or NumPy or equivalent, and producing plots and summaries.
  • Experience interpreting PD metrics and performing QoR analysis and debugging.
  • Practical debugging skills and ability to communicate technical findings clearly.
  • Team-player attitude, responsible, and self-motivated.
  • Nice to have: experience with partition-level back-end flows (RTL to GDS), STA collaboration, chiplet design, and developing lightweight automation or AI-assisted tools.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, or an Electrical Practical Engineer certificate, or equivalent practical experience.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-05-15