Physical Design Engineer

Job Title

Physical Design Engineer

Role Summary

Hands-on physical design engineer responsible for RTL-to-GDSII implementation and signoff for SoC/ASIC projects. The role focuses on floorplanning, placement, CTS, routing, timing closure, and verification to achieve tapeout readiness on advanced process nodes.

Onsite in Santa Clara, CA; full-time or long-term contract engagement, working closely with RTL, DFT, STA and backend teams.

Experience Level

Mid-level — 5–15 years of relevant physical design experience.

Responsibilities

Primary responsibilities include physical implementation, timing and signoff activities across chip and block levels.

• Execute full-chip and block-level physical design (floorplanning, placement, CTS, routing).
• Drive timing closure, congestion analysis, and power optimization.
• Perform physical verification and signoff checks (DRC/LVS, signoff extraction workflows).
• Analyze and resolve setup/hold violations and signal integrity issues (IR drop, EM).
• Support low-power implementation techniques and ECO flows; coordinate UPF/CPF flows as needed.
• Collaborate with RTL, DFT, STA, and backend teams to reach tapeout readiness for advanced nodes.

Requirements

Key technical skills and experience required; preferred items are listed separately.

• Proven experience with physical design flow from netlist to GDSII.
• Expertise in floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
• Hands-on experience with signoff and implementation tools (examples: Cadence Innovus, Synopsys ICC2, PrimeTime, Tempus, Mentor/Calibre).
• Knowledge of static timing analysis (STA), IR drop and EM analysis, and DRC/LVS verification flows.
• Strong scripting skills (Tcl, Perl, or Python) for automation and debug.
• Strong debugging and problem-solving abilities; experience driving design closure on complex blocks/SoCs.
• Preferred: experience with low-power methodologies, UPF/CPF flows, prior tapeout on complex SoCs, and experience on advanced nodes (7nm/5nm/3nm).

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.